Interrupt Window means a specific timing that a processor can inject an interrupt. On Intel VT-x, there is an option to intercept Interrupt Window by setting the bit in Primary Processor-based VM-Execution Control field in VMCS. However, there isn’t such an option on AMD-V.

If we take a look at the layout of VMCB, we may observe that AMD-V provides a virtual local APIC mechanism for you to inject virtual interrupts. The interception vector 3 also provides interception of virtual interrupt. These two combined are actually making you intercepting interrupt window. The workflow is:

1. Use the virtual Local APIC to inject a virtual interrupt (Set the V_IRQ bit). If you would like to intercept interrupt window regardless of TPR, set the V_IGN_TPR bit in order to let the virtual interrupt ignore the virtual TPR. Or otherwise you can intercept an interrupt window with a specific TPR.
2. Intercept the virtual interrupts by setting VINTR interception bit. The processor cannot take the virtual interrupt until the rflags.if is set and the TPR meets the priority requirements. Therefore, the interception is exactly the moment of interrupt window.
3. You may realize that this is actually even more advanced than Intel VT-x in that, on Intel VT-x, you will need to intercept accesses to the cr8 register in order to virtualize TPR.

On Zen 4 processors, you can materialize intercepting NMI-window on AMD-V in the similar fashion. Note that you can’t simply treat iret instruction as NMI-window opportunity since on later implementations of AMD64 architecture, a new MSR called EXCP_IN_PROG is used to prevent re-entrance of exceptions. This MSR is effective against NMI by masking it when the corresponding bit is set. So even if the iret instruction is executed, it does not necessarily mean the NMI-window is incoming. Also, wrmsr instruction could also mean an NMI-window if it is trying to reset the bit in EXCP_IN_PROG MSR.